Consumers demand that their mobile devices have sufficient battery life. But the clocking rate and throughput for mobile device processors continues to grow as well, which exacerbates the power demands on battery life. To provide sufficient battery life in light of these demands, additional power savings must be obtained from the various mobile device components.
A significant factor for mobile device battery life is the power consumption from the mobile device's embedded memories. Embedded memories occupy a relatively large amount of die space in a mobile device integrated circuit such as a system-on-a-chip (SOC). The resulting dynamic power for embedded memories may be a substantial portion of the overall power consumption of a given device. For example, it is conventional to precharge both bit lines in a corresponding bit line pair for each write cycle in an embedded static random access memory (SRAM). One of the bit lines in the bit line pair is then discharged responsive to the binary value to be written to a bitcell coupled to the bit line pair in the write cycle. The precharging and subsequent discharging of the bit lines contributes significantly to the embedded SRAM's dynamic power consumption.
There is thus a need in the art for improved SRAM architectures that provide reduced dynamic power consumption.